The present invention relates to a method and apparatus for improving step height performance in a chemical mechanical planarization (CMP) process for semiconductor wafers. More particularly, the present invention relates to a method and apparatus for improving CMP performance by pre-conditioning the polishing pad surface finish.
Semiconductor wafers are typically fabricated with multiple copies of a desired integrated circuit design that will later be separated and made into individual chips. A common technique for forming the circuitry on a semiconductor wafer is photolithography. Part of the photolithography process requires that a special camera focus on the wafer to project an image of the circuit on the wafer. The ability of the camera to focus on the surface of the wafer is often adversely affected by inconsistencies or unevenness in the wafer surface. This sensitivity is accentuated with the current drive for smaller, more highly integrated circuit designs which cannot tolerate certain nonuniformities within a particular die or between a plurality of dies on a wafer. Because semiconductor circuits on wafers are commonly constructed in layers, where a portion of a circuit is created on a first layer and conductive vias connect it to a portion of the circuit on the next layer, each layer can add or create nonuniformity on the wafer that must be smoothed out before generating the next layer.
Chemical mechanical planarization (CMP) techniques are used to planarize the raw wafer and each layer of material added thereafter. Available CMP systems, commonly called wafer polishers, often use a rotating wafer holder that brings the wafer into contact with a polishing pad moving in the plane of the wafer surface to be planarized. In some systems, a polishing fluid, such as a chemical polishing agent or slurry containing microabrasives, is applied to the polishing pad to polish the wafer. The wafer holder then presses the wafer against the rotating polishing pad and is rotated to polish and planarize the wafer. Some available wafer polishers use a linear belt rather than a rotating surface to carry the polishing pad.
With use, the polishing pads used in standard, chemical slurry CMP systems become smoothed and clogged with used slurry and debris from the polishing process. The accumulation of debris reduces the surface roughness and adversely affects polishing rate and uniformity. Polishing pads are typically conditioned to roughen the pad surface, provide microchannels for slurry transport, and remove debris or byproducts generated during the CMP process. Standard methods for conditioning this type of polishing pad may use a rotary disk embedded with diamond particles to roughen the surface of the polishing pad.
A goal of CMP for semiconductor wafers is to reduce the final step height of polished features on the semiconductor wafers. For example, integrated circuits are commonly built using a method known as Shallow Trench Isolation (STI). In STI, one circuit is isolated from another by creating a trench between the adjacent circuits and filling it with an insulator. The trench is known as a field and the circuit regions are known as the active regions. The insulator often is deposited or spun on uniformly over the field and active regions, and chemical mechanical planarization is subsequently used to flatten the surface.
Ideally, the higher topology regions (active regions) should be polished without polishing the lower topology regions (field). One problem with current CMP systems is that they can cause dishing on wafers where not only the higher, active regions on a wafers are polished, but the lower field regions are also polished so that an undesirably large xe2x80x9cstep heightxe2x80x9d remains between the active and field regions. Additionally, there is a need to reliably characterize a CMP process so that the improved step height performance may be repeated. Accordingly, further development of an apparatus and method for reducing step height variation and characterizing performance of equipment used in the chemical mechanical planarization of semiconductor wafers is desired.